PReFECT
Predictable Multiprocessor Platforms for Embedded Safety Critical Systems
| POCI-01-0145-FEDER-029119 PTDC/CCI-COM/29119/2017 30 months (Jul 2018 to Jan 2021) | |
| Summary: | The PReFECT project will address the following challenges with respect to the introduction of multicore processors in safety-critical systems: - model and analyze the timing interference generated by the hardware resources shared between cores (e.g., caches, interconnect and I/O devices); - propose runtime mechanisms and scheduling solutions to mitigate the unpredictability of COTS multicore processors by controlling the interference between cores; - develop tools for the automatic system configuration before its deployment. The goal of this task is to optimize the usage of the platform while guaranteeing that all the timing requirements of the applications are respected. To attain these objectives we will build upon the large body of results already published by the research team on modelling and timing analysis of multicore processors, and on the expertise of the industrial partners (GMV and Critical Software) in the safety critical system development. The project results will be demonstrated in two industrial use-cases related to the avionics and automotive domains. |
| Funding: | Global: 237KEUR, CISTER: 237KEUR |
| Sponsors: |     |
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| Contact Person at CISTER: | Eduardo Tovar |
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Conference or Workshop Papers
Design and implementation of an FPGA-based NoC for Real Time Systems CISTER-TR-190510
Yilian Ribot, Geoffrey NelissenWork in Progress Session, 31st Conference on Real-Time Systems (ECRTS 2019). 9 to 13, Jul, 2019, pp 1-3. Stuttgart, Germany.https://www.ecrts.org/wp-content/uploads/2019/06/ECRTS2019-WIP-proceedings.pdf
Yilian Ribot, Geoffrey NelissenWork in Progress Session, 31st Conference on Real-Time Systems (ECRTS 2019). 9 to 13, Jul, 2019, pp 1-3. Stuttgart, Germany.https://www.ecrts.org/wp-content/uploads/2019/06/ECRTS2019-WIP-proceedings.pdf
PDFResilienceP Analysis: Bounding Cache Persistence Reload Overhead for Set-Associative Caches CISTER-TR-190512
Syed Aftab Rashid, Geoffrey Nelissen, Eduardo TovarWork in Progress Session, 31st Conference on Real-Time Systems (ECRTS 2019). 9 to 13, Jul, 2019, pp 7-9. Stuttgart, Germany.https://www.ecrts.org/wp-content/uploads/2019/06/ECRTS2019-WIP-proceedings.pdf
Syed Aftab Rashid, Geoffrey Nelissen, Eduardo TovarWork in Progress Session, 31st Conference on Real-Time Systems (ECRTS 2019). 9 to 13, Jul, 2019, pp 7-9. Stuttgart, Germany.https://www.ecrts.org/wp-content/uploads/2019/06/ECRTS2019-WIP-proceedings.pdf
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation CISTER-TR-180604
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2018). 28 to 31, Aug, 2018, Session 4: Support for Predictability, pp 111-117. Hakodate, Japan.
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2018). 28 to 31, Aug, 2018, Session 4: Support for Predictability, pp 111-117. Hakodate, Japan.